RISC-V. Part 5: J-Link

1 Download and Install the J-Link Software

Download and install an appropriate version of the J-Link software. It installs to /opt/SEGGER/JLink which is a symbolic link from /opt/SEGGER/JLink_V672d.

2 Firmware Upgrade

Before using the probe, update its firmware to the most recent version using /opt/SEGGER/JLink/JLinkConfigExe.

3 Connecting with Outdated Probes

When J-Trace revision 3.2 and J-Link EDU 8 were built, there was no RISC-V. They do not work. The request to connect with a J-Trace 3.2 ends with the messages:

⋮
Detected: RV32 core
CSR access via abs. commands: No
ConfigTargetSettings() start
ConfigTargetSettings() end
TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Cannot connect to target.

4 Connecting with Recent Probes

Connect a J-Link EDU version 11.0 to the host and start the JLinkExe utility:

./JLinkExe

SEGGER J-Link Commander V6.72d (Compiled May 15 2020 16:50:13)
DLL version V6.72d, compiled May 15 2020 16:50:03

Connecting to J-Link via USB...O.K.
Firmware: J-Link V11 compiled Apr 23 2020 16:49:23
Hardware version: V11.00
S/N: 261005761
License(s): FlashBP, GDB
OEM: SEGGER-EDU
VTref=0.000V


Type "connect" to establish a target connection, '?' for help

To turn the power on, enter:

power on

The “Target power” LED turns on and the development board powers up.

device risc-v
speed 1000

Selecting 1000 kHz as target interface speed

si jtag

Selecting JTAG as current target interface.

con

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Device "RISC-V" selected.


Connecting to target via JTAG
ConfigTargetSettings() start
ConfigTargetSettings() end
TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Debug architecture:
  RISC-V debug: 0.13
  AddrBits: 7
  DataBits: 32
  IdleClks: 7
Memory access:
  Via system bus: No
  Via ProgBuf: Yes (2 ProgBuf entries)
DataBuf: 4 entries
  autoexec[0] implemented: Yes
Detected: RV32 core
CSR access via abs. commands: No
Temp. halted CPU for NumHWBP detection
HW instruction/data BPs: 4
Support set/clr BPs while running: No
HW data BPs trigger before execution of inst
RISC-V identified.

5 Firmware Backup

From the J-Link>-prompt backup binary data from internal FLASH:

savebin /tmp/rv32.bin,0,20000

Opening binary file for writing... [/tmp/rv32.bin]
Reading 131072 bytes from addr 0x00000000 into file...O.K.

verifybin /tmp/rv32.bin ,0

Loading binary file /tmp/rv32.bin
Reading 131072 bytes data from target memory @ 0x00000000.
Verify successful.

6 What’s Next?

To really start developing, we need the following setup:

We have made a giant step. All the blue parts have been verified:

• The hardware (PC, Probe and Target) is running.
• The interfacing (USB and JTAG) works.
• The J-Link firmware connects to the RISC-V target and we can read and write FLASH memory. DFU — as a workaround — is no longer required.

What is still missing is the glue between the debugger (gdb) and the probe: OpenOCD. This will be solved in the next blog.

RISC-V. Part 4: JTAG Cabling

1 The SeeedStudio Connector

Compared to the development board, the standard 20-pin 0.1″ JTAG connector is huge. Therefore, SeeedStudio created another proprietary 0.1″ JTAG 10-pin connector. ☹!

The pin assignment is documented in the schematics and in pinout. The same pins are duplicated on the GPIO headers:

GPIO Header			JTAG Header
Signal	Port	PIN	Signal	PIN
GND	GND	H2/41
GND	GND	H2/42
JTDI	PA15	H3/1	TDI	5
JTMS	PA13	H3/3	TMS	7
NJTRST	PB4	H3/5	TRST	3
JTCK	PA14	H3/2	TCK	9
JTDO	PB3	H3/4	TDO	6
NRST	NRST	H3/6	NRST	4
GND	GND	H3/34	GND	10
3V3	3V3	H2/{43…48}1	3V3	1…2
5V		H3/{45…48}2

¹ Continuity tested to AMS1117 voltage regulator (pin 2).

² Continuity tested to AMS1117 voltage regulator (pin 3).

2 The J-Link Connector

J-Link / J-Trace use a popular connector. It is documented in J-Link / J-Trace User Guide, Software Version: 6.70, Date: May 7, 2020, section 18.1.1 Pinout for JTAG:

PIN	SIGNAL	TYPE	Description
1	VTref	Input	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from VDD of the target board and must not have a series resistor.
2	Not connected	NC	This pin is not connected in J-Link.
3	nTRST	Output	JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
5	TDI	Output	JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of the target CPU.
7	TMS	Output	JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of the target CPU.
9	TCK	Output	JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of the target CPU.
11	RTCK	Input	Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13	TDO	Input	JTAG data output from target CPU. Typically connected to TDO of the target CPU.
15	nRESET	I/O	Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called “nRST”, “nRESET” or “RESET”. This signal is an active low signal.
17	DBGRQ	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
19	5V-Supply	Output	This pin can be used to supply power to the target hardware. Older J-Links may not be able to supply power on this pin. For more information about how to enable/disable the power supply, please refer to Target power supply.
4, 6, 8, 10, 12	GND		GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

3 Wiring

Waste of effort is always brought about by missing interfaces. Though having a box full of JTAG/SWD cables and adaptors with 0.05″/0.1″ spacing and 10/16/20/38 pins none of them fits. Later I found an adapter which can be googled by TQ2440 mini2440 (or “ULink2 JTAG ARM Adapter 20Pin 2+2.54 mm 14Pin 2.54mm 10P 2+2.54mm 6P + 10P XH2.54”). It almost does the job.

JLink		Color	Dev Board		Adapter TQ2440 mini2440	JTAG
Signal	Pin		Signal	Pin	Pin	Signal
GND	4	blue	GND	H2/41	10	GND
GND	6	blue	GND	H2/42	10	GND
5V	19	red	5V	H3/48
VTref	1	white	3V3	H2/47	1…2	3V3
nTRST	3	brown	NJTRST	H3/5	3	TRST
TDI	5	yellow	JTDI	H3/1	5	TDI
TMS	7	orange	JTMS	H3/3	7	TMS
TCK	9	green	JTCK	H3/2	9	TCK
TDO	13	grey	JTDO	H3/4	6	TDO
nRESET	15	violet	NRST	H3/6	4	NRST

Until the adapter arrived I had to do it the hard way:

Debugging the SeeedStudio GD32 RISC-V Dev Board

4 Power-Up the Target

“Almost” (in the last section) means that the target is not powered by the adaptor. For that, the red 5V cable must still be plugged in and, as described in the next blog, the line must be enabled.