RISC-V. Part 5: J-Link

1 Download and Install the J-Link Software

Download and install an appropriate version of the J-Link software. It installs to /opt/SEGGER/JLink which is a symbolic link from /opt/SEGGER/JLink_V672d.

2 Firmware Upgrade

Before using the probe, update its firmware to the most recent version using /opt/SEGGER/JLink/JLinkConfigExe.

3 Connecting with Outdated Probes

When J-Trace revision 3.2 and J-Link EDU 8 were built, there was no RISC-V. They do not work. The request to connect with a J-Trace 3.2 ends with the messages:

⋮
Detected: RV32 core
CSR access via abs. commands: No
ConfigTargetSettings() start
ConfigTargetSettings() end
TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Cannot connect to target.

4 Connecting with Recent Probes

Connect a J-Link EDU version 11.0 to the host and start the JLinkExe utility:

./JLinkExe

SEGGER J-Link Commander V6.72d (Compiled May 15 2020 16:50:13)
DLL version V6.72d, compiled May 15 2020 16:50:03

Connecting to J-Link via USB...O.K.
Firmware: J-Link V11 compiled Apr 23 2020 16:49:23
Hardware version: V11.00
S/N: 261005761
License(s): FlashBP, GDB
OEM: SEGGER-EDU
VTref=0.000V


Type "connect" to establish a target connection, '?' for help

To turn the power on, enter:

power on

The “Target power” LED turns on and the development board powers up.

device risc-v
speed 1000

Selecting 1000 kHz as target interface speed

si jtag

Selecting JTAG as current target interface.

con

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Device "RISC-V" selected.


Connecting to target via JTAG
ConfigTargetSettings() start
ConfigTargetSettings() end
TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Debug architecture:
  RISC-V debug: 0.13
  AddrBits: 7
  DataBits: 32
  IdleClks: 7
Memory access:
  Via system bus: No
  Via ProgBuf: Yes (2 ProgBuf entries)
DataBuf: 4 entries
  autoexec[0] implemented: Yes
Detected: RV32 core
CSR access via abs. commands: No
Temp. halted CPU for NumHWBP detection
HW instruction/data BPs: 4
Support set/clr BPs while running: No
HW data BPs trigger before execution of inst
RISC-V identified.

5 Firmware Backup

From the J-Link>-prompt backup binary data from internal FLASH:

savebin /tmp/rv32.bin,0,20000

Opening binary file for writing... [/tmp/rv32.bin]
Reading 131072 bytes from addr 0x00000000 into file...O.K.

verifybin /tmp/rv32.bin ,0

Loading binary file /tmp/rv32.bin
Reading 131072 bytes data from target memory @ 0x00000000.
Verify successful.

6 What’s Next?

To really start developing, we need the following setup:

We have made a giant step. All the blue parts have been verified:

• The hardware (PC, Probe and Target) is running.
• The interfacing (USB and JTAG) works.
• The J-Link firmware connects to the RISC-V target and we can read and write FLASH memory. DFU — as a workaround — is no longer required.

What is still missing is the glue between the debugger (gdb) and the probe: OpenOCD. This will be solved in the next blog.